The present invention relates to a device for chucking a semiconductor wafer and a method for stripping a semiconductor wafer, which are both arranged to electrostatically absorb the semiconductor wafer and strip it.
With the recent advance of a drying process in a process for manufacturing a semiconductor and larger diameter of the wafer, more uniform working has been required. For this purpose, it is necessary to positively fix and install the wafer on a wafer platform.
For example, in a reactive ion etching (as referred to as RIE, hereinafter) apparatus for dry-etching a wafer placed on an electrode where a high frequency is applied, the wafer is easily heated by plasma, so that a rise in a wafer temperature may thermally impair a photoresist for an etching mask or worsen the etched shape. To avoid these disadvantages, it is necessary to cool down the wafer being etched to a necessary temperature. For this purpose, the wafer is required to be hermetically held on the high frequency applied electrode controlled at a given temperature.
As such means for holding the wafer, in addition to a mechanical type or a vacuum type apparatus, an electrostatic chuck has been used wherein a dc electrode is buried in the lower portion of a wafer platform with a dielectric material therebetween so that the wafer makes a close contact with the placing surface of the high frequency applied electrode by virtue of electrostatic force. It has been well known that the electrostatic chuck is advantageous in making the wafer more tabular, usability in a vacuum chamber, and processability of an overall plane of the wafer surface. However, though the wafer can be efficiently cooled down by strong absorption, when stripping the wafer off the placing surface after etching the wafer, the charges left in a dielectric film cause residual absorption which prevents easy stripping of the wafer. For overcoming this shortcoming in stripping, various kinds of methods have been put into practise (for example, JP-A-159744/1990, JP-A-271286/1992 and JP-A-291194/1993).
Next, the prior art will be concretely described below. FIG. 5 is a sectional view showing a treatment chamber provided in the conventional leaf treating type parallel plate RIE apparatus. The apparatus shown in FIG. 5 includes a grounded vacuum vessel 8, a gas inlet 7 for feeding given amounts of reactive gas and inert gas into the vacuum vessel 8, a wafer platform 1 having a wafer placed thereon where a high frequency power is applied, a grounded opposed electrode 10 having pores from which reactive and inert gases are blown, a high frequency power source 5 for generating plasma between the wafer platform 1 and the opposed electrode 10, a grounded wafer lift pin 3 for lifting up the wafer 2 to a position where the wafer 2 is stripped off the wafer platform 1 and carried out of the vacuum vessel 8, and an ESC power source 9 for applying a given ac voltage overlapped with the high frequency onto the wafer platform 1 for fixing the wafer 2 on the wafer platform 1 by electrostatic absorption.
The wafer platform 1, as shown in FIG. 6, contains the ESC electrode 16 buried therein so that the dc voltage may be applied from the ESC power source 9 to the ESC electrode 16.
Next, the operation will be described. When the wafer lift pin 3 is located at a top dead center, the wafer 2 is carried out of the vacuum vessel 8 by a vacuum carrying robot 2 or the like to a given position on the wafer lift pin 3. Then, the wafer lift pin 3 is descended to a bottom dead center, where the wafer is placed on the center of the water placing surface of the wafer platform 1 controlled at a given temperature.
In this state, as keeping the inside of the vacuum vessel 8 at a given pressure, the reactive gas is fed from the gas inlet 7 at a given flow rate and the ESC power source 9 and the high frequency power source 5 are both operated, when the plasma is generated between the wafer platform 1 and the opposed electrode 10. By keeping this state for a certain time, the predetermined RIE treatment is completed. On completion of the RIE treatment, the ESC power source 9 is stopped and the reactive gas atmosphere inside the vacuum vessel 8 is replaced with inert gas for reducing or removing the residual absorption caused between the wafer 2 and the wafer platform 1. The wafer lift pushes the wafer 2 from the wafer placing surface of the wafer platform 1 to the carrying position, and then the wafer 2 is carried out of the vacuum vessel 8 by the vacuum carrying robot or the like. This is a completion of the series of operations.
In turn, the description will be oriented to means for stripping the wafer 2 absorbed on the wafer placing surface of the wafer platform 1 off the wafer placing surface after the completion of the required RIE treatment with reference to FIG. 7. FIG. 7 is a flowchart showing an operation executed in stripping the wafer.
On the completion of the RIE treatment (step 201), the ESC power source 9 is stopped (step 202). Then, the gas being fed to the vacuum vessel 8 is switched from the reactive gas to the inert gas (step 203). The supply power from the high frequency power source 5 is lowered to the allowable minimum power for generating the plasma (as referred to as de-charging plasma, hereinafter) (step 204). Next, the high frequency power source 5 is stopped (step 205). These series of operations result in lowering a negative self-biased voltage occurring on the wafer 2, thereby suppressing extra etching to a minimum and reducing the residual electrostatic absorption.
Then, after the wafer lift pin 3 is moved up to the top dead point (steps 206 and 207), the wafer 2 is naturally stripped off the wafer placing surface and then is moved up to the carrying position (step 209). Further, by grounding the wafer lift pin 3 only in the operation of the apparatus (step 208), without losing the high frequency power applied in the RIE treatment, the residual charges between the rear side of the wafer 2 and the wafer platform 1 are discharged to the grounding side for further reducing the residual absorption. These series of operations results in implementing the highly reliable stripping of the wafer 2.
However, in the conventional wafer stripping system disclosed in JP-A-159744/1990, JP-A-27128619/1992 and JP-A-291194/1993, in stripping the wafer, the wafer 3 located on the wafer lift pin 2 is inclined or is bounced from the wafer lift pin 2. This action may move the wafer 3 out of a given place of the wafer lift pin 3, which leads to breakage of the wafer.
The grounds of the above phenomenon will be described along the prior arts. In the wafer stripping system described in JP-A-158744/1990, the wafer 2 held on the wafer platform 1 is forcibly stripped off the wafer platform by a wafer lift pin located on the center of the wafer platform 1 and a swing cam for lifting up the wafer 2 from the outer peripheral portion of the wafer platform 2 in concert with the pushup action of the wafer lift pin 3 located on the peripheral portion of the wafer platform 1. In the wafer stripping system described in JP-A-271286/1992, the wafer lift pin 3 or a pressurized gas injecting port is located on the outer peripheral portion of the wafer platform 1 so that the wafer 2 may be stripped off the wafer platform 1 by virtue of small force. In either system, the wafer 2 is forcibly stripped off the wafer platform 1 without reducing the residual absorption caused between the wafer 2 and the wafer platform 1. Hence, if the large residual charges are left if an oxide film is laid on the rear surface of the wafer, part of the wafer 2 is kept held on the wafer platform 1 in stripping. Hence, when the wafer 2 on the wafer lift pin 3 is inclined or part of the wafer 2 held on the wafer platform 1 overcomes the residual charges, the wafer 2 may be stripped off the wafer platform 1, when the repulsion may take place so that the repulsion may make the wafer 2 bounce.
In the wafer stripping system described in JP-A-291194/1993, after completion of the required etching, only the ESC power source 9 is stopped as keeping the high frequency power source 5 in operation. The residual charges corresponding to the supply voltage of the ESC power source 9 is lowered to the residual charges corresponding to the self-biasing voltage obtained by the de-charging plasma caused by the supply of the high frequency power, thereby reducing the residual absorption. This reduction makes it possible for the wafer 2 to be easily stripped off the wafer platform 1. However, when the higher frequency power is applied for the required etching treatment, the self-biasing voltage becomes greater than or the same as the the ESC power voltage 9, which eliminates the effect of reducing the residual absorption.
Further, in the wafer stripping system described in JP-A-291194/1993 and the foregoing prior, in the process of lifting up the wafer 2 from the wafer platform 1 by the wafer lift pin 3, since the wafer 2 is grounded through the wafer lift pin 3 while the wafer lift pin 3 is in contact with the wafer 2, the charges left between the wafer 2 and the wafer platform 1 are discharged to the grounding side through the wafer lift pin 3, thereby further reducing the residual absorption and improving the stripping characteristic. The creation of the insulating material generated in the RIE treatment adheres to the portion of the wafer lift pin 3 contacting with the wafer 2 with time. The deposition of the reactive creation serves to insulate the wafer 2 from the wafer lift pin 3, that is, keep the wafer 2 out of the grounding contact with the wafer lift pin 3. As a result, the charges left between the wafer 2 and the wafer platform 1 are disallowed to be discharged, thereby disabling to reduce the residual absorption.
In the wafer stripping system described in the foregoing prior arts and JP-A-291194/1993, the in-plane uniformity of the etching portion is made worse. This is because any of the foregoing prior arts is arranged to stop only the ESC power source 9 and generate the de-charging plasma from the high frequency power while the high frequency power source is in operation after the completion of the given etching treatment, for proceeding the overflown etching whose wafer in-plane uniformity is worse by the de-charging plasma.